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FEATURES Full 14-Bit Performance 5 V Single Supply Operation Low Power Fast Settling Time Unbuffered Voltage Output Capable of Driving 60 k Loads Directly SPITM/QSPITM/MICROWIRETM-Compatible Interface Standards Power-On Reset Clears DAC Output to 0 V (Unipolar Mode) Schmitt Trigger Inputs for Direct Optocoupler Interface APPLICATIONS Digital Gain and Offset Adjustment Automatic Test Equipment Data Acquisition Systems Industrial Process Control
5 V, Serial-Input Voltage-Output, 14-Bit DACs AD5551/AD5552
FUNCTIONAL BLOCK DIAGRAMS
VDD
AD5551
VREF 14-BIT DAC VOUT
AGND CS DIN SCLK CONTROL LOGIC SERIAL INPUT REGISTER 14-BIT DATA LATCH
DGND
VDD
AD5552
RINV VREFF 14-BIT DAC
RFB RFB INV
VOUT AGNDF
GENERAL DESCRIPTION
VREFS CS LDAC SCLK DIN CONTROL LOGIC SERIAL INPUT REGISTER
The AD5551 and AD5552 are single, 14-bit, serial input, voltage output DACs that operate from a single 5 V 10% supply. The AD5551 and AD5552 utilize a versatile 3-wire interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. These DACs provide 14-bit performance without any adjustments. The DAC output is unbuffered, which reduces power consumption and offset errors contributed by an output buffer. With an external op amp the AD5552 can be operated in bipolar mode generating a VREF output swing. The AD5552 also includes Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. For higher precision applications, please refer to 16-bit DACs AD5541, AD5542, and AD5544. The AD5551 and AD5552 are available in an SO package.
14-BIT DATA LATCH AGNDS
DGND
PRODUCT HIGHLIGHTS
1. Single Supply Operation. The AD5551 and AD5552 are fully specified and guaranteed for a single 5 V 10% supply. 2. Low Power Consumption. Typically 1.5 mW with a 5 V supply. 3. 3-Wire Serial Interface. 4. Unbuffered output capable of driving 60 k loads, which reduces power consumption as there is no internal buffer to drive. 5. Power-On Reset Circuitry.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD5551/AD5552-SPECIFICATIONS T = T
Parameter STATIC PERFORMANCE Resolution Relative Accuracy, INL Differential Nonlinearity Gain Error Gain Error Temperature Coefficient Zero Code Error Zero Code Temperature Coefficient AD5552 Bipolar Resistor Matching Bipolar Zero Offset Error Bipolar Zero Temperature Coefficient OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough DAC Output Impedance Power Supply Rejection Ratio DAC REFERENCE INPUT Reference Input Range Reference Input Resistance2 LOGIC INPUTS Input Current VINL, Input Low Voltage VINH, Input High Voltage Input Capacitance3 Hysteresis Voltage3 REFERENCE Reference -3 dB Bandwidth Reference Feedthrough Signal-to-Noise Ratio Reference Input Capacitance POWER REQUIREMENTS VDD IDD Power Dissipation 2.0 9 7.5 0 -VREF 1 25 10 10 6.25 1.0 VDD Min 14 0.15 0.15 -1.75 -0.3 0.1 0 0.1 0.05 1.0 0.8 0 0.5 Typ Max
(VDD = 5 V 10%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications A MIN to TMAX, unless otherwise noted.)
Unit Bits LSB LSB LSB ppm/C LSB ppm/C / % LSB ppm/C V V s V/s nV-s nV-s k LSB V k k A V V pF V MHz mV p-p dB pF pF All 1s Loaded All 0s Loaded, VREF = 1 V p-p at 100 kHz Code 0000H Code 3FFFH Test Condition
B Grade Guaranteed Monotonic
1.000 0.0015 0.0152 0.25 2.5 0.2 VREF - 1 LSB VREF - 1 LSB
RFB/RINV, Typically RFB = RINV = 28 k Ratio Error
Unipolar Operation AD5552 Bipolar Operation to 1/2 LSB of FS, CL = 10 pF CL = 10 pF, Measured from 0% to 63% 1 LSB Change Around the Major Carry All 1s Loaded to DAC, VREF = 2.5 V Tolerance Typically 20% VDD 10%
Unipolar Operation AD5552, Bipolar Operation
1 0.8 2.4 10 0.4 1.3 1 92 75 120 4.50 0.3 1.5 5.50 1.1 6.05
V mA mW
NOTES 1 Temperature range is as follows: B Version: -40C to +85C. 2 Reference input resistance is code-dependent, minimum at 2555 H. 3 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
-2-
REV. 0
AD5551/AD5552 TIMING CHARACTERISTICS1, 2 otherwise noted.)
Parameter fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Limit at TMIN, TMAX All Versions 25 40 20 20 15 15 35 20 15 0 30 30 30
(VDD = 5 V
5%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless
Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Description SCLK Cycle Frequency SCLK Cycle Time SCLK High Time SCLK Low Time CS Low to SCLK High Setup CS High to SCLK High Setup SCLK High to CS Low Hold Time SCLK High to CS High Hold Time Data Setup Time Data Hold Time LDAC Pulsewidth CS High to LDAC Low Setup CS High Time Between Active Periods
NOTES 1 Guaranteed by design. Not production tested. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90% of +3 V and timed from a voltage level of +1.6 V). Specifications subject to change without notice.
t1
SCLK
t6 t4
CS
t2
t3 t7
t5
t 12 t8 t9
DB13 DB0
DIN
t 11
LDAC*
*AD5552 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
t 10
Figure 1. Timing Diagram
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-3-
AD5551/AD5552
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V Digital Input Voltage to DGND . . . . . -0.3 V to VDD + 0.3 V VOUT to AGND . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V AGND, AGNDF, AGNDS to DGND . . . . . -0.3 V to +0.3 V Input Current to Any Pin Except Supplies . . . . . . . . 10 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature, (TJ max) . . . . . . . . . 150C
Package Power Dissipation . . . . . . . . . . . . . (TJ max - TA)/JA Thermal Impedance JA SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . 149.5C/W SOIC (R-14) . . . . . . . . . . . . . . . . . . . . . . . . . . 104.5C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD5551BR AD5552BR
Die Size = 80
INL 1 LSB 1 LSB
DNL 0.8 LSB 0.8 LSB
Temperature Range -40C to +85C -40C to +85C
Package Description 8-Lead Small Outline IC 14-Lead Small Outline IC
Package Option SO-8 R-14
139 = 11,120 sq mil; Number of Transistors = 1230.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5551/AD5552 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD5551 PIN FUNCTION DESCRIPTIONS
Mnemonic VOUT AGND VREF CS SCLK DIN DGND VDD
Pin No. 1 2 3 4 5 6 7 8
Description Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry. This is the voltage reference input for the DAC. Connect to external reference ranges from 2 V to VDD. This is an active low-logic input signal. The chip select signal is used to frame the serial data input. Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK. Digital Ground. Ground reference for digital circuitry. Analog Supply Voltage, 5 V 10%.
AD5551 PIN CONFIGURATION SOIC
VOUT 1 AGND 2
8
AD5552 PIN CONFIGURATION SOIC
RFB 1 VOUT 2 AGNDF 3 AGNDS 4
14 13 12
VDD DGND
VDD INV DGND LDAC
AD5551
7
TOP VIEW VREF 3 (Not to Scale) 6 DIN CS 4
5
SCLK
AD5552
11
TOP VIEW VREFS 5 (Not to Scale) 10 DIN VREFF 6 CS 7
9 8
NC SCLK
NC = NO CONNECT
-4-
REV. 0
AD5551/AD5552
AD5552 PIN FUNCTION DESCRIPTIONS
Mnemonic RFB VOUT AGNDF AGNDS VREFS VREFF CS SCLK NC DIN LDAC DGND INV VDD
TERMINOLOGY Relative Accuracy
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Description Feedback Resistor. In bipolar mode connect this pin to external op amp output. Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry (Force). Ground Reference Point for Analog Circuitry (Sense). This is the voltage reference input (sense) for the DAC. Connect to external reference ranges from 2 V to VDD. This is the voltage reference input (force) for the DAC. Connect to external reference ranges from 2 V to VDD. This is an active low-logic input signal. The chip select signal is used to frame the serial data input. Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. No Connect. Serial Data Input. This device accepts 14-bit words. Data is clocked into the input register on the rising edge of SCLK. LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. Digital Ground. Ground reference for digital circuitry. Connected to the Internal Scaling Resistors of the DAC. Connect INV pin to external op amps inverting input in bipolar mode. Analog Supply Voltage, 5 V 10%.
Digital-to-Analog Glitch Impulse
For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL versus code plot can be seen in TPC 1.
Differential Nonlinearity
Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. A plot of the glitch impulse is shown in TPC 14.
Digital Feedthrough
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. TPC 4 illustrates a typical DNL versus code plot.
Gain Error
Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal.
Gain Error Temperature Coefficient
Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. CS is held high, while the CLK and DIN signals are toggled. It is specified in nV-s and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. A typical plot of digital feedthrough is shown in TPC 13.
Power Supply Rejection Ratio
This is a measure of the change in gain error with changes in temperature. It is expressed in ppm/C.
Zero Code Error
This specification indicates how the output of the DAC is affected by changes in the power supply voltage. Power-supply rejection ratio is quoted in terms of % change in output per % change in VDD for full-scale output of the DAC. VDD is varied by 10%.
Reference Feedthrough
Zero code error is a measure of the output error when zero code is loaded to the DAC register.
Zero Code Temperature Coefficient
This is a measure of the change in zero code error with a change in temperature. It is expressed in mV/C.
This is a measure of the feedthrough from the VREF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in mV p-p.
REV. 0
-5-
AD5551/AD5552-Typical Performance Characteristics
0.5 TA = 25 C VDD = 5V VREF = 2.5V 0.25
0.25 0.5 TA = 25 C VDD = 5V VREF = 2.5V
INL - LSB
0
DNL - LSB
0
-0.25
-0.25
-0.5
0
2048
4096
6144
8192
10240
12288 14336 16384
-0.5
0
2048
4096
6144
8192
10240
12288 14336 16384
CODE - Decimal
CODE - Decimal
TPC 1. Integral Nonlinearity vs. Code
TPC 4. Differential Nonlinearity vs. Code
0.5 VDD = 5V VREF = 2.5V 0.25
0.5 VDD = 5V VREF = 2.5V 0.25
0
DNL - LSB
-20 20 60 TEMPERATURE - C 100 140
INL - LSB
0
-0.25
-0.25
-0.5 -60
-0.5 -60
-20
20 60 TEMPERATURE - C
100
140
TPC 2. Integral Nonlinearity vs. Temperature
TPC 5. Differential Nonlinearity vs. Temperature
1.0 0.75 VREF = 2.5V TA = 25 C DNL
LINEARITY ERROR - LSB
0.5 VDD = 5V TA = 25 C DNL 0.25
LINEARITY ERROR - LSB
0.5 0.25 0 -0.25 -0.5 -0.75 -1.0
0
INL
INL -0.25
2
3
4 5 SUPPLY VOLTAGE - V
6
7
-0.5 0
1
2 3 4 REFERENCE VOLTAGE
5
6
TPC 3. Linearity Error vs. Supply Voltage
TPC 6. Linearity Error vs. Reference Voltage
-6-
REV. 0
AD5551/AD5552
1.00 0.75 0.50
GAIN ERROR - LSB
0.75 VDD = 5V VREF = 2.5V VDD = 5V VREF = 2.5V
ZERO-CODE OFFSET ERROR - LSB 150
0.50
0.25 0 -0.25 -0.50 -0.75 -1.00 -50
0.25
-25
0
25
50
75
100
125
0 -50
-25
0
25
50
75
100
125
150
TEMPERATURE - C
TEMPERATURE - C
TPC 7. Gain Error vs. Temperature
TPC 10. Zero-Code Error vs. Temperature
250 VDD = 5V VLOGIC = 5V VREF = 2.5V
A
A
450 TA = 25 C 400
SUPPLY CURRENT -
SUPPLY CURRENT -
350
200
300
REFERENCE VOLTAGE VDD = 5V
SUPPLY VOLTAGE VREF = 2.5V
250
200
150 -40
150
-20
0
20 40 60 TEMPERATURE - C
80
100
120
0
1
2
3 VOLTAGE - V
4
5
6
TPC 8. Supply Current vs. Temperature
TPC 11. Supply Current vs. Reference Voltage or Supply Voltage
400 VDD = 5V VREF = 2.5V TA = 25 C
300 1555H 250 0155H 2155H TA = 25 C VDD = 5V VREF = 2.5V BIPOLAR MODE
REFERENCE CURRENT - A
350
SUPPLY CURRENT - A
200
300
150 UNIPOLAR MODE 100
250
200
50
150
0
1
3 2 DIGITAL INPUT VOLTAGE - V
4
5
0
0
2048
4096
6144
8192
10240
12288 14336 16384
CODE - Decimal
TPC 9. Supply Current vs. Digital Input Voltage
TPC 12. Reference Current vs. Code
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-7-
AD5551/AD5552
100 90
CLOCK (5V/DIV)
VREF = 2.5V VDD = 5V TA = 25 C
2s/DIV
100 90
CS (5V/DIV) 10pF 50pF 100pF 200pF
VOUT (50mV/DIV)
10 0%
10 0%
VREF = 2.5V VDD = 5V TA = 25 C VOUT (0.5V/DIV)
2 s/DIV
TPC 13. Digital Feedthrough
VREF = 2.5V VDD = 5V TA = 25 C
TPC 15. Large Signal Settling Time
VREF = 2.5V VDD = 5V TA = 25 C
100 90
100 90
VOUT (1V/DIV)
CS (5V/DIV)
VOUT (0.1V/DIV)
10 0% 10 0%
VOUT (50mV/DIV) GAIN = -216
2s/DIV
0.5 s/DIV
TPC 14. Digital-to-Analog Glitch Impulse
GENERAL DESCRIPTION
TPC 16. Small Signal Settling Time
The AD5551/AD5552 are single, 14-bit, serial input, voltage output DACs. They operate from a single supply ranging from 2.7 V to 5 V and consume typically 300 A with a supply of 5 V. Data is written to these devices in a 14-bit word format, via a 3- or 4-wire serial interface. To ensure a known power-up state, these parts were designed with a power-on reset function. In unipolar mode, the output is reset to 0 V, while in bipolar mode, the AD5552 output is set to -VREF. Kelvin sense connections for the reference and analog ground are included on the AD5552.
Digital-to-Analog Section
With this type of DAC configuration, the output impedance is independent of code, while the input impedance seen by the reference is heavily code dependent. The output voltage is dependent on the reference voltage as shown in the following equation.
VOUT = VREF x D 2N
where D is the decimal data word loaded to the DAC register and N is the resolution of the DAC. For a reference of 2.5 V, the equation simplifies to the following.
The DAC architecture consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 2. The DAC architecture of the AD5551/AD5552 is segmented. The four MSBs of the 14-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either AGND or VREF. The remaining 10 bits of the data word drive switches S0 to S9 of a 10-bit voltage mode R-2R ladder network.
R R VOUT 2R 2R S0 VREF 2R S1 2R S9 2R E1 2R E2 2R E15
VOUT =
2.5 x D 16 , 384
giving a VOUT of 1.25 V with midscale loaded, and 2.5 V with full-scale loaded to the DAC. The LSB size is VREF/16,384.
Serial Interface
10-BIT R-2R LADDER
FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS
Figure 2. DAC Architecture
The AD5551 and AD5552 are controlled by a versatile 3-wire serial interface, which operates at clock rates up to 25 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. The timing diagram can be seen in Figure 1. Input data is framed by the chip select input, CS. After a high-to-low transition on CS, data is shifted synchronously and latched into the input register on the rising edge of the serial clock, SCLK. Data is loaded MSB first in 14-bit words. After 14 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the DAC. Data can only be loaded to the part while CS is low. -8- REV. 0
AD5551/AD5552
The AD5552 has an LDAC function that allows the DAC latch to be updated asynchronously by bringing LDAC low after CS goes high. LDAC should be maintained high while data is written to the shift register. Alternatively, LDAC may be tied permanently low to update the DAC synchronously. With LDAC tied permanently low, the rising edge of CS will load the data to the DAC.
Unipolar Output Operation
2.5V 5V 0.1 F 10 F 0.1 F
RFB SERIAL INTERFACE VDD CS DIN SCLK LDAC DGND RINV VREFF VREFS RFB INV OUT
+5V
These DACs are capable of driving unbuffered loads of 60 k. Unbuffered operation results in low-supply current, typically 300 A, and a low-offset error. The AD5551 provides a unipolar output swing ranging from 0 V to VREF. The AD5552 can be configured to output both unipolar and bipolar voltages. Figure 3 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table I.
5V 2.5V 10 F
AD5551/AD5552
AGNDF AGNDS -5V EXTERNAL OP AMP
BIPOLAR OUTPUT
Figure 4. Bipolar Output (AD5552 Only)
Table II. Bipolar Code Table
DAC Latch Contents MSB LSB 11 1111 1111 10 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 1111 0000 0001 0000 0000
Analog Output +VREF x (8191/8192) +VREF x (1/8192) 0V -VREF x (1/8192) -VREF x (8191/8192) = -VREF
0.1 F
0.1 F
SERIAL INTERFACE
VDD CS DIN SCLK LDAC*
VREFF*
VREFS*
AD5551/AD5552
OUT
AD820/ OP196
EXTERNAL OP AMP
UNIPOLAR OUTPUT
DGND
* AD5552 ONLY
AGND
Assuming a perfect reference, the worst-case bipolar output voltage may be calculated from the following equation. Bipolar Mode Worst-Case Output
VOUT - BIP =
Figure 3. Unipolar Output
Table I. Unipolar Code Table
[(V
OUT -UNI
+ VOS 2 + RD - VREF 1 + RD
)( ) 1 + (2 + RD) / A
(
)]
DAC Latch Contents MSB LSB 11 1111 1111 10 0000 0000 00 0000 0000 00 0000 0000 1111 0000 0001 0000
Analog Output VREF x (16383/16384) VREF x (8192/16384) = 1/2 VREF VREF x (1/16384) 0V
where VOS = External Op Amp Input Offset Voltage RD = RFB and RIN Resistor Matching Error, Unitless A = Op Amp Open-Loop Gain
Output Amplifier Selection
Assuming a perfect reference, the worst-case output voltage may be calculated from the following equation. Unipolar Mode Worst-Case Output VOUT -UNI = where VOUT-UNI D VREF VGE VZSE INL D x (VREF + VGE ) + VZSE + INL 214
For bipolar mode, a precision amplifier should be used, supplied from a dual power supply. This will provide the VREF output. In a single-supply application, selection of a suitable op amp may be more difficult as the output swing of the amplifier does not usually include the negative rail, in this case AGND. This can result in some degradation of the specified performance unless the application does not use codes near zero. The selected op amp needs to have very low-offset voltage, (the DAC LSB is 152 V with a 2.5 V reference), to eliminate the need for output offset trims. Input bias current should also be very low as the bias current multiplied by the DAC output impedance (approximately 6K) will add to the zero code error. Rail-to-rail input and output performance is required. For fast settling, the slew rate of the op amp should not impede the settling time of the DAC. Output impedance of the DAC is constant and code-independent, but in order to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds another time constant to the system, hence increasing the settling time of the output. A higher 3 dB amplifier bandwidth results in a faster effective settling time of the combined DAC and amplifier.
= Unipolar Mode Worst-Case Output = Decimal Code Loaded to DAC = Reference Voltage Applied to Part = Gain Error in Volts = Zero Scale Error in Volts = Integral Nonlinearity in Volts
Bipolar Output Operation
With the aid of an external op amp, the AD5552 may be configured to provide a bipolar voltage output. A typical circuit of such operation is shown in Figure 4. The matched bipolar offset resistors RFB and RINV are connected to an external op amp to achieve this bipolar output swing where RFB = RINV = 28 k. Table II shows the transfer function for this output operating mode. Also provided on the AD5552 are a set of Kelvin connections to the analog ground inputs.
REV. 0
-9-
AD5551/AD5552
Force Sense Buffer Amplifier Selection
These amplifiers can be single-supply or dual supplies, lownoise amplifiers. A low-output impedance at high frequencies is preferred as they need to be able to handle dynamic currents of up to 20 mA.
Reference and Ground
FO
LDAC** CS DIN SCLK
ADSP-2101/ ADSP-2103*
TFS DT SCLK
AD5551/ AD5552*
As the input impedance is code-dependent, the reference pin should be driven from a low-impedance source. The AD5551/ AD5552 operates with a voltage reference ranging from 2 V to VDD. Although DAC's full-scale output voltage is determined by the reference, references below 2 V will result in reduced accuracy. Tables I and II outline the analog output voltage for particular digital codes. For optimum performance, Kelvin sense connections are provided on the AD5552. If the application does not require separate force and sense lines, they should be tied together close to the package to minimize voltage drops between the package leads and the internal die. ADR291 and ADR293 are suitable references for this product.
Power-On Reset
*ADDITIONAL PINS **AD5552 ONLY
OMITTED FOR CLARITY.
Figure 5. ADSP-2101/ADSP-2103 to AD5551/AD5552 Interface
68HC11 to AD5551/AD5552 Interface
Figure 6 shows a serial interface between the AD5551/AD5552 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC, while the MOSI output drives the serial data lines SDIN. CS signal is driven from one of the port lines. The 68HC11 is configured for master mode; MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI output is valid on the rising edge of SCK.
These parts have a power-on reset function to ensure the output is at a known state upon power-up. On power-up, the DAC register contains all zeros, until data is loaded from the serial register. However, the serial register is not cleared on power-up, so its contents are undefined. When loading data initially to the DAC, 14 bits or more should be loaded to prevent erroneous data appearing on the output. If more than 14 bits are loaded, only the last 14 are kept, and if fewer than 14 are loaded, bits will remain from the previous word. If the AD5551/AD5552 needs to be interfaced with data shorter than 14 bits, the data should be padded with zeros at the LSBs.
Power Supply and Reference Bypassing
PC6
LDAC** CS DIN SCLK
68HC11/ 68L11*
PC7 MOSI SCK
AD5551/ AD5552*
*ADDITIONAL PINS OMITTED FOR CLARITY. **AD5552 ONLY
Figure 6. 68HC11/68L11 to AD5551/AD5552 Interface
MICROWIRE to AD5551/AD5552 Interface
For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor.
MICROPROCESSOR INTERFACING
Figure 7 shows an interface between the AD5551/AD5552 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD5551/ AD5552 on the rising edge of the serial clock. No glue logic is required as the DAC clocks data into the input shift register on the rising edge.
CS CS DIN SCLK
Microprocessor interfacing to the AD5551/AD5552 is via a serial bus that uses standard protocol compatible with DSP processors and microcontrollers. The communications channel requires a 3-wire interface consisting of a clock signal, a data signal and a synchronization signal. The AD5551/AD5552 requires a 14-bit data word with data valid on the rising edge of SCLK. The DAC update may be done automatically when all the data is clocked in or it may be done under control of LDAC (AD5552 only).
ADSP-2101/ADSP-2103 to AD5551/AD5552 Interface
MICROWIRE*
SO SCLK
AD5551/ AD5552*
*ADDITIONAL
PINS OMITTED FOR CLARITY.
Figure 7. MICROWIRE to AD5551/AD5552 Interface
80C51/80L51 to AD5551/AD5552 Interface
Figure 5 shows a serial interface between the AD5551/AD5552 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set to operate in the SPORT (Serial Port) transmit alternate framing mode. The ADSP-2101/ADSP-2103 is programmed through the SPORT control register and should be configured as follows: Internal Clock Operation, Active Low Framing, 16-Bit Word Length. The first 2 bits are DON'T CARE as AD5551/AD5552 will keep the last 14 bits. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. Because of the edges-triggered difference, an inverter is required at the SCLKs between the DSP and the DAC.
A serial interface between the AD5551/AD5552 and the 80C51/ 80L51 microcontroller is shown in Figure 8. TxD of the microcontroller drives the SCLK of the AD5551/AD5552, while RxD drives the serial data line of the DAC. P3.3 is a bit programmable pin on the serial port which is used to drive CS.
P3.4 LDAC** CS DIN SCLK
80C51/ 80L51*
P3.3 RxD TxD
AD5551/ AD5552*
*ADDITIONAL PINS **AD5552 ONLY
OMITTED FOR CLARITY.
Figure 8. 80C51/80L51 to AD5551/AD5552 Interface
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REV. 0
AD5551/AD5552
The 80C51/80L51 provides the LSB first, while the AD5551/ AD5552 expects the MSB of the 14-bit word first. Care should be taken to ensure the transmit routine takes this into account. Usually it can be done through software by shifting out and accumulating the bits in the correct order before inputting to the DAC. Also, 80C51 outputs 2 byte words/16 bits data, thus the first two bits, after rearrangement, should be DON'T CARE as they will be dropped from the DAC's 14-bit word. When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is valid on the falling edge of TxD, so the clock must be inverted as the DAC clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 transmits its data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. As the DAC requires a 14-bit word, P3.3 (or any one of the other programmable bits) is the CS input signal to the DAC, so P3.3 should be brought low at the beginning of the 16-bit write cycle 2 x 8 bit words and held low until the 16-bit 2 x 8 cycle is completed. After that, P3.3 is brought high again and the new data loads to the DAC. Again, the first two bits, after rearranging, should be DON'T CARE. LDAC on the AD5552 may also be controlled by the 80C51/80L51 serial port output by using another bit programmable pin, P3.4.
APPLICATIONS Optocoupler interface Decoding Multiple AD5551/AD5552s
The CS pin of the AD5551/AD5552 can be used to select one of a number of DACs. All devices receive the same serial clock and serial data, but only one device will receive the CS signal at any one time. The DAC addressed will be determined by the decoder. There will be some digital feedthrough from the digital input lines. Using a burst clock will minimize the effects of digital feedthrough on the analog signal channels. Figure 10 shows a typical circuit.
AD5551/AD5552 SCLK CS DIN VDD DIN SCLK VOUT
ENABLE CODED ADDRESS
EN DECODER
AD5551/AD5552 CS DIN SCLK DGND AD5551/AD5552 CS DIN SCLK VOUT VOUT
The digital inputs of the AD5551/AD5552 are Schmitttriggered, so they can accept slow transitions on the digital input lines. This makes these parts ideal for industrial applications where it may be necessary that the DAC is isolated from the controller via optocouplers. Figure 9 illustrates such an interface.
AD5551/AD5552 CS DIN SCLK
VOUT
5V REGULATOR POWER
Figure 10. Addressing Multiple AD5551/AD5552s
10 F 0.1 F
VDD 10k SCLK SCLK VDD
VDD
AD5551/AD5552
10k CS CS VOUT
VDD 10k DIN DIN GND
Figure 9. AD5551/AD5552 in an Optocoupler Interface
REV. 0
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AD5551/AD5552
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SO (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
14-Lead SO (R-14)
0.3444 (8.75) 0.3367 (8.55) 0.1574 (4.00) 0.1497 (3.80)
14 1 8 7
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1
0.0500 (1.27) BSC 0.0196 (0.50) 0.0099 (0.25) 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 45
0.050 (1.27) BSC
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
45
0.0098 (0.25) 0.0040 (0.10) SEATING PLANE
0.0098 (0.25) 0.0040 (0.10)
8 0 0.0192 (0.49) SEATING 0.0099 (0.25) 0.0138 (0.35) PLANE 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
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REV. 0
PRINTED IN U.S.A.
C01943-5-7/00 (rev. 0)

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